The present invention generally relates to a semiconductor apparatus having high-frequency and high-output semiconductor elements, which is used for, for example, radiocommunication equipment and so on, and a process for producing the same. Particularly, the present invention relates to via holes used in such a semiconductor apparatus and a process for fabricating the via holes.
Semiconductor apparatuses disclosed in JP-A-59-94818 and JP-A-8-279562 have a substrate having a front surface and a back surface, semiconductor elements formed on the front surface of the substrate, and a backside metal layer formed on the back surface of the substrate. The semiconductor apparatus is also provided with via holes passing through the substrate in proximity of the semiconductor elements. At least one electrode of each semiconductor element is connected to the backside metal layer through a metal wiring within each via hole. Thereby, the wiring resistance and the inductance of the semiconductor apparatus are reduced compared with the case where a package is connected to semiconductor elements with Au wires.
In a semiconductor apparatus having high-frequency and high-output semiconductor elements, it has been an important task to carry out a reduction in the grounding inductance and the heat resistance. A high grounding inductance would cause the deterioration of the high-frequency characteristics. Further, if the heat resistance is high, device characteristics will become unstable due to the self-heat of the elements generated when operating.
In order to reduce the grounding inductance and the heat resistance, a construction has been proposed in which metal wirings are formed within via holes passing through a substrate, and electrodes of high-frequency and high-output elements are connected to the wirings within the via holes, thus connecting a backside metal layer provided on the backside of the substrate to the electrodes.
As a process for producing a semiconductor apparatus, there has hitherto been a method in which dry etching according to a reactive ion etching (“RIE”) method using chlorine gas is performed to form, as shown in FIG. 10, etching holes 267 for forming via holes in a substrate 201 in proximity of high-frequency, high-output elements 200 as shown in FIG. 10. Thereafter, although not shown, via holes are formed using the etching holes 267 by polishing the backside of the substrate 201.
In the conventional process for producing a semiconductor apparatus, if the depth of the etching holes 267 increases, the etching rate is varied depending on the crystal orientation of the substrate 201, and side walls of the etching holes 267 become oblique with respect to the top surface of the substrate 201. This is because of the following reasons: if the depth of the etching holes 267 increases, the ion density in plasma decreases during the dry etching process, and a chemical reaction due to ions is decelerated, resulting in the deterioration of the vertical processability, which is characteristic of the RIE method. Accordingly, the etching shape becomes similar to that obtained by wet etching.
In this way, the deeper the etching holes 267, the narrower the width of the etching holes 267 towards the backside. Therefore, when the opening size of the etching holes 267 at the front-surface is small, it is not possible to increase the depth of the etching holes 267. As a result, there is a problem in that deep via holes with a small opening size at the front-surface side cannot be formed using the etching holes 267.